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d a t a sh eet product speci?cation file under integrated circuits, ic02 august 1991 integrated circuits TDA8433 deflection processor for computer controlled tv receivers
august 1991 2 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 features i 2 c-bus interface input for vertical sync sawtooth generator with amplitude independent of frequency vertical deflection output stage driver east-west raster correction drive output eht modulation input changes picture width and height without affecting geometry. general description the TDA8433 is an i 2 c-bus controlled deflection processor which, together with a sync processor (e.g. tda2579a, see fig.6), contains the control and drive functions of the deflection part in a computer controlled tv receiver. the TDA8433 replaces all picture geometry settings which were previously set manually during manufacture. quick reference data note to quick reference data 1. vr in = 0; v-s-corr = 0; v shift = 20 h; v ampl = 20 h. ordering information note 1. sot101-1; 1996 december 2. symbol parameter min. typ. max. unit v cc supply voltage (pin 12) 10.8 12.0 13.2 v i cc supply current (pin 12) 12 20 27 ma v 2 vertical sync trigger level - 3 - v v 21 vertical feedback (note 1) dc level - 1.7 1.85 2.05 v ac level 1.65 1.8 1.95 v p v 24 eht compensation operating range 1.7 - 6v v 11-13 inputs for control register data: not locked to video - 0.7 1 v at 50 hz status 0.8 v cc -- v at 60 hz status -- 0.7 v cc v v 10-13 hcent comparator switching level - v 17 - v v 14-13 sda i 2 c-bus switching level data input - 3.5 - v v 15 scl i 2 c-bus switching level clock input - 3.5 - v v 1 device selection where: ao = '1' 9.0 - v cc v ao = '0' 0 - 2.0 v extended type number package pins pin position material code TDA8433 24 dil plastic sot101 (1)
august 1991 3 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.1 block diagram.
august 1991 4 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 pinning pin description 1 ao subaddress 2 vertical sync input 3 vertical blanking output 4i ref resistor 5 vertical blanking/?yback timing capacitor 6 dacc (tau switching) 7 dacb (horizontal phase) 8 daca (horizontal frequency) 9 out (video switch) 10 i/o (f o adjustment) 11 in (hlockn - 50/60 hz) 12 positive supply +12 v 13 ground 1 14 serial data input 15 serial clock input 16 internal supply voltage 17 voltage reference for i/o 18 ground 2 (waveform) 19 east-west drive output 20 vertical drive output 21 vertical feedback 22 vertical sawtooth capacitor 23 vertical amplitude capacitor 24 eht input fig.2 pinning diagram.
august 1991 5 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 pin functions pin 1 - ao subaddress the ao bit is the least significant bit of the bus-address. it enables two TDA8433s, with different addresses, to be connected to the same bus. pin 2 - vertical sync input positive trigger pulses of > 3 v are sufficient to exceed the internal threshold of the ramp generator. flyback and blanking will then start and, during the blanking period, the circuit will be inhibited for further input pulses (see fig.3). it should be noted that the TDA8433 has no vertical oscillator therefore, the sync processor, which is used in this combination, has to provide trigger pulses as well when the video input is absent. pin 3 - vertical blanking the positive going blanking pulse is fed from a current source. the blanking period is fixed by the capacitor connected to pin 5 and the resistor connected to pin 4 (see fig.3). pins 4 and 5 - reference/?yback timing the external resistor connected between pin 4 and ground provides a reference current for the triangle generator circuit. this circuit generates the triangle waveform at pin 5. the width of the blanking pulse is set by the external capacitor connected to pin 5. table 1 sync processor time constants vtra vtrc output time constant '0' '0' 12 v automatic operation '0' '1' 5.3 v medium '1' '0' 1.5 v fast (video recorder) '1' '1' 0.2 v not to be used pin 6 - dacc (tau switching) the output voltage, which depends on the vtra and vtrc bits in the i 2 c-bus control register, is connected to the coincidence detector of the sync processor. in this way the time constants of the horizontal pll (in the sync processor) can be set. if the tda2579 is used (see fig.6) the effect will be as listed in table 1. pin 7 - dacb (horizontal phase) the voltage at pin 7 is fed to the horizontal pulse modulator in the sync processor. this voltage, together with the signal produced by the phase 2 detector during horizontal flyback, sets the phase of the horizontal output with respect to the flyback pulse in the horizontal output stage. the voltage range is variable between 0.05 v and 10 v. pin 8 - daca (horizontal frequency) the frequency of the horizontal oscillator in the external sync processor is adjusted by the voltage level at pin 8. the voltage is variable in 63 steps from 0.05 v to 10 v (i.e. 0.158 v per step). pin 9 - out (video switch) the output at pin 9 is controlled by the cvbs bit from the control register where cvbs = logic 0; the output is high (open collector) cvbs = logic 1; the output is low (saturation voltage) an external video selector can be controlled by means of this switching function. pins 10 and 17 - i/o and voltage reference pin 10 is connected to the output of the phase 1 detector in the sync processor. whether the pin is used as an input or an output is dependent on the phi1 bit of the horizontal frequency (hfreq) register. when phi = logic 0 (output transistor open) pin 10 is used as an input. the dc information at this pin is compared with the reference voltage at pin 17 and is reflected in the hcent of the status register. hcent = logic 0; input > v ref at v 17 hcent = logic 1; input < v ref at v 17 in this way the free running frequency can be adjusted by computer while the oscillator is locked. alternatively, when phi1 = logic 1, pin 10 is switched to ground. the free running frequency of the oscillator can the be adjusted while watching the screen provided that pin 10 is connected to the video input of the sync processor. pin 11 -in (hlockn and 50/60 hz) this pin is connected to the combined mute and 50/60 hz pin of the sync processor. the various dc levels define the state of the hlockn and 50/60 hz bits in the status register (see table 2.)
august 1991 6 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 table 2 status register bits state of sync processor (tda2579) typical voltage at pin 11 state of hlockn 50/60 hz not locked to computer video < 0.7 v(min.) '1' '0' 60 hz transmitter found 0.7 to 0.75 v cc '0' '0' 50 hz transmitter found > 0.75 v cc to v cc '0' '1' pin 12 - positive supply (12 v) the nominal supply voltage at pin 12 is 12 v which should remain within the defined limits. the nominal current consumption is 20 ma. pins 13 and 18 - ground (1 and 2) ground 1 (pin 13) is for the bus transceiver section ground 2 (pin 18) is for the sawtooth and picture geometry control section. pins 14 and 15 - sda and scl (serial data and serial clock) input serial data is applied to pin 14. the serial clock input from the i 2 c-bus is applied to pin 15. pin 16 - internal supply voltage (+5 v) in some applications it may be necessary to connect a capacitor to this pin to avoid interference. pin 19 - east-west drive output the output drive for the east-west correction circuit has a nominal range from 1.6 to 11.7 v and contains 5 programmable parameters (see fig.5). the parameters are: picture width east-west raster correction east-west trapezium correction east-west corner correction compensation for eht variations pins 20 and 21 - vertical drive output and vertical feedback input the vertical comparator and drive output stage is designed so that the feedback signal applied to pin 21 can be inverted in the comparator by the v-out control bit. this enables the use of two different vertical output stages. one output stage is without an internal comparator (e.g. tda3654). the feedback signal at pin 21 has a negative slope during scan. during power-up the ic is adapted (preset) for this type of output stage. the other output stage contains a comparator. the drive for this output stage is obtained by interconnecting pins 20 and 21 and switching the v-out polarity. the v-out bit will then be set to logic 1. in both cases the drive signal available at pin 20 contains 5 parameters which can be set via the i 2 c-bus control; picture height vertical linearity vertical s-correction vertical shift extent of compensation for eht variations (see fig.4.) pins 22 and 23 - vertical sawtooth/vertical amplitude capacitor the 100 nf capacitor connected to pin 22 is charged and discharged by two current sources in the vertical ramp generator. in order to obtain an equal amplitude, at different frequencies, an amplitude comparator has been incorporated. the circuit, together with the 330 nf capacitor connected to pin 23, keeps the sawtooth amplitude at reference voltage level (7.1 v). the external load of the amplitude stabilization loop of pin 23 should be as low as possible. the recommended value is 3 500 m w . pin 24 - eht input (modulation) a voltage between 1.7 and 6 v (depending on the eht variations) applied to pin 24 will modulate the amplitude of the vertical drive sawtooth and the east-west drive output. in this way the effect of beam current variations can be virtually eliminated. i 2 c-bus control the addresses for the i 2 c-bus are 100011ao0 (write) and 100011ao1 (read). the inclusion of the ao bit makes it possible to control two different deflection processors. after receiving the address byte the i 2 c-bus transmits its status byte in which the status of the control bits is contained. ponres - power-on-reset after switch-on, or a power dip below 6.7 v, the ponres bit is set to logic 1. after a status read operation ponres is reset to logic 0.
august 1991 7 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 hlockn - horizontal lock this bit indicates whether the horizontal oscillator in the sync processor is locked to the video signal. when the oscillator is locked hlockn is set to logic 0 (v 11 > 0.7 v). when the oscillator is not locked hlockn is set to logic 1 (v 11 < 0.7 v). hcent - horizontal centre this bit is set to logic 0 when the horizontal oscillator frequency is too high (v 10 > v ref ). the bit is set to logic 1 when the frequency is too low v 10 < v ref ). in - 50/60 hz the voltage at pin 11 also contains the 50/60 hz information where: logic 0 = v 11 0.75 v cc (60 hz or no transmitter) logic 1 = 3 v 11 0.75 v cc (50 hz) the sequence of data in the status byte is: ponres, hlockn, 50/60 hz, 0 0 0 0. a write operation starts with address byte 100011ao0. the device is then ready to receive the subaddress byte e.g. trapezium (hexoa) 00001010 followed by the data byte e.g. hex20. the dac will then set the trapezium correction signal into the selected position (see fig.5). if more data bytes follow within one transmission then, by means of an auto-increment, the next highest subaddress will be selected. wrap-around occurs after hexof. table 3 registers function sub addr hex data bits preset value hex sett hex min. typ. max. unit h-frequency 00 phi-x-6 01 00 3f - 9.5 0.05 10 0.2 11 v v h-phase 01 6 01 00 3f - 9.5 0.05 10 0.2 11 v v picture height v 21/20 02 6 01 00 3f - + 15 - 19 + 19 - 22 - % % v-linearity 03 6 01 00 3f 0 13 - 17 1 21 % % v-s correction 04 6 01 00 3f 0 15 - 19 1 - % % v-shift 05 6 01 00 3f +17 - 17 +19 - 19 +22 + 22 % % v-compensation v 24 = 1.7 v 06 5 01 00 1f tbf - 8 0 - 10 - - 12 - % picture width 07 6 01 00 3f - 6.0 1.6 6.6 2.4 7.2 v v e-w parabola (reg: 07 = 0) 08 6 01 00 3f - 7.0 0.07 7.5 0.1 8.5 v v e-w corner (reg: 08 = 3f) 09 6 01 00 3f - 1.7 0 2.2 tbf 2.8 v v trapezium reg: 07 = 00; 08 = 20h 0a 6 01 00 3f 0.75 1.0 1.25 1.9 - - v v h-compensation reg. 07 = 00; 08 = 0; 09 = 00 v 24 = 1.7 v 0b 5 01 00 1f 0 - tbf 10 - - % %
august 1991 8 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 note to table 3 1. tbf = value to be fixed. limiting values in accordance with the absolute maximum system (iec 134) thermal resistance not used 0c/0e -- ---- control 0f x-vout - 40 11.5 11.9 v cc v vtra - vtrc - 50 5.0 5.3 5.6 v cvbs - x - x - x - 60 1.2 1.5 1.8 v 70 0 0.2 0.5 v 40 5.5 7.5 9.5 k w 50 2.4 3.3 4.2 k w 60 0.7 1.0 1.35 k w 70 - 50 -w 00 -- (vbs) v 08 -- 0.4 (1 ma) v phi1 bit 00 1 - 80 -- 0.4 ( - 2 ma) v 00 -- v cc v not used 10 - ef test functions f0 - ff symbol parameter min. max. unit v cc supply voltage 10.8 13.2 v i cc supply current 12 27 ma p tot total power dissipation - 360 mw t amb operating ambient temperature range - 25 +75 c t stg storage temperature range - 55 +150 c symbol parameter typ. max. unit r th j-a from junction to ambient in free air - 35 k/w function sub addr hex data bits preset value hex sett hex min. typ. max. unit
august 1991 9 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 characteristics v cc = 12 v; v 24 = 1/2 x v cc ;t amb = 25 c; unless otherwise speci?ed symbol parameter conditions min. typ. max. unit supplies v cc supply voltage (pin 12) 10.8 12.0 13.2 v i cc supply current (pin 12) 12 20 27 ma ao subaddresses (pin 1) v 1 switching level allowed voltage for a o = 0 note 1 - - 2.3 - - 2 v v for ao = '1' 9 - v cc v i 1 input current -- +10 m a v 1 not allowed voltage range 2.0 - 8.9 v vertical sync input (pin 2) v 2 switching level 2.5 3.0 3.5 v i 2 current during non-active state v 2 = 0 v - 310 m a vertical blanking output (pin 3) v 3(p-p) pulse amplitude (peak-to-peak value) 1 ma load -- v cc - 2v v 3 output voltage 1 ma load 10.0 10.5 - v i o output source current 1 -- ma t w pulse width r 4 = 75 k w c 5 = 8.2 nf - 1.13 - ms reference (pin 4) v 4 reference voltage 6.8 7.15 7.5 v i 4 current range 90 - 150 m a vertical blanking timing (pin 5) v 5(p-p) amplitude of triangular pulse (peak-to-peak value) r 4 = 75 k w c 5 = 8.2 nf 7.5 7.9 8.3 v t w width of triangular pulse - 1.3 - ms i 5 sink current v 5 = 3.5 v; i 4 = 100 m a 85 105 125 m a i 5 source current v 5 = 3.5 v; i 4 = 100 m a 80 100 120 m a dacc output (pin 6) v 6 voltages at vtr(a) and vtr(c) where: (a) = '0'; (c) = '0' 11.5 11.9 - v (a) = '0'; (c) = '1' 5.0 5.3 5.6 v (a) = '1'' (c) = '0' 1.2 1.5 1.8 v (a) = '1'; (c) = '1' 0 0.2 0.5 v
august 1991 10 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 dacc output (pin 6) z 6 output impedance at vtr(a) and vtr(c) where: (a) = '0'; (c) = '0' 5.5 7.5 9.5 k w (a) = '0'; (c) = '1' 2.4 3.3 4.2 k w (a) = '1'; (c) = '0' 0.7 1.0 1.35 k w (a) = '1'; (c) = '1' - 50 -w dacb horizontal phase (pin 7) v 7 output voltage at hex00 - 0.05 0.2 v at hex3f 9.4 10.0 11.0 v d v 7 variable dc output voltage for setting horizontal frequency 0.05 - 10 v r 7 internal resistance - 0.3 1.0 k w step size note 3 10 - 190 % rr ripple rejection 26 -- db daca horizontal frequency (pin 8) v 8 output voltage at hex00 - 0.05 0.2 v at hex3f 9.5 10.0 11.0 v d v 8 variable dc output voltage for setting horizontal frequency 0.05 - 10 v r 8 internal resistance - 0.3 1.0 k w step size note 3 10 - 190 % rr ripple rejection 26 -- db out video switch (pin 9) f or external cvbs switch when cvbs bit =1 v 9 saturation voltage i sink = 1 ma -- 0.4 v i l leakage current -- 2 m a i/o combined input/output (pin 10) v 10 when used as an output (open collector) where phi1 = '0' -- v cc v where phi1 = '1' -- 0.4 v i sink sink current -- 2ma v 10 when used as an input (switching point hcent is '0' to '1') phi1 = '0' v 17 - 35 mv v 17 v 17 + 35 mv v i 10 input current -- 2 m a symbol parameter conditions min. typ. max. unit
august 1991 11 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 in hlockn and 50/60 hz (pin 11) v 11 hlockn switching level - 0.7 - v v 11 switching level where: lockn = '0' 1.0 -- v lockn = '1' -- 0.4 v v 11 switching level where: 50/60 hz = '0' -- 0.7 v cc v 50/60 hz = '1' state 50 hz 0.8 v cc -- v i 11 source current 10 25 35 m a sda serial data input (pin 14) v 14 switching level where: sda = 0 -- 1.5 v sda = 1 3.0 -- v i 14 sink current - 0.5 10 m a scl serial clock input (pin 15) v 15 switching level where: sda = 0 -- 1.5 v sda = 1 3.0 -- v i 15 sink current - 0.5 10 m a internal supply voltage v 16 maximum allowed load 1 ma load 4.5 5.0 5.5 v v 17 voltage reference for pin 10 (pin 17) 1.0 - v cc - 1.5 v i 17 input load current -- 2.0 m a e-w drive output (pin 19; see application information) v 19 output voltage 1 ma load 0.5 - 11.5 v i 19 output current 1.0 - 2.0 ma rr ripple rejection 24 30 - db r i internal resistance - 12k w t r response time - 2 -m s vertical drive output (pin 20; see application information) v 20 output voltage 1 ma load 0.5 - 10.5 v i 20 output current 1.5 2.0 - ma rr ripple rejection note 2 35 40 - db dac stepsize note 3 10 - 190 % vertical feedback (pin 21; see application information: register 02 = 20h, 03 = 0, 04 = 0, 05 = 20h, 06 = 0) v 21 dc input voltage 1.7 1.85 2.05 v v 21(p-p) ac output voltage (peak-to-peak value) note 2 1.65 1.8 1.95 v i 21 input current -- - 3 m a symbol parameter conditions min. typ. max. unit
august 1991 12 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 notes to the characteristics 1. outside the test mode. 2. test condition (hex values): register 02 = 3f; 03 = 00; 04 = 00; 05 = 20; 06 = 00; v 22 = 1/2 v 4 ; f = 50 hz to 30 khz. 3. 4. applies to both modes. 5. external load of this pin (leakage current capacitor etc.) should be 3 500 m w . vertical sawtooth voltage (pin 22; see application information) v 22 top level of sawtooth 6.7 7.1 7.4 v v 22 minimum level of sawtooth i sink = 0.5 ma -- 50 mv i 22 discharge sink current v 22 = 3.5 v 6.5 9.5 15 ma i 22 charge source current v 23 =5v; v 22 = 3.5 v 120 35 m a i 22 control range 5 v to 1 v 80 135 190 m a z 22 ac impedance - 3 - m w c ext external capacitance - 100 - nf vertical sawtooth stabilizer (pin 23; see application information) i 23 discharge sink current v 22 = 2 v 200 250 300 m a i 23 charge source current v 22 = 9.75 v 185 235 285 m a c ext external capacitance - 390 - nf i l leakage current note 5 -- 0.015 m a eht modulation input (pin 24; see application information) v 24 voltage operating range 1/7 v cc - 1/2 v cc v i 24 input current - 0.5 2.0 m a symbol parameter conditions min. typ. max. unit value stepn value stepn C 1 C average step size ---------------------------------------------------------------------------------- 100% 63>n>1 () .
august 1991 13 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.3 vertical sawtooth timing.
august 1991 14 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.4 vertical raster-corrections.
august 1991 15 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.5 east-west raster-corrections.
august 1991 16 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.6 application diagram (continued in fig.7).
august 1991 17 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.7 application diagram (continued from fig.6).
august 1991 18 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 application information the formulae from which the typical vertical drive and typical e-w drive waveforms are generated are given in the following sub-paragraphs. for this purpose a typical application diagram for the vertical drive stage is assumed to be as illustrated in fig.7. pin 20 is the vertical drive output which drives an inverting power amplifier. the feedback network, r1 to r4 and c1 and c2, has two functions; to transfer the voltage on the feedback pin (pin 21) to a voltage across the feedback resistor r1 to stabilize the voltage across c1 at a fixed value. for this typical application the formula for the vertical scan waveform refers to the voltage at pin 21. the formula for the e-w drive waveform refers to the voltage at pin 19. all dac variables that control the vertical and e-w drive waveforms are normalized. each dac is defined as having a control range between 0 and 1. the 0 corresponds to a register value of hex00 and the 1 to a maximum value of hex1f (for a 5-bit dac) or hex3f (for a 6-bit dac). table 4 dac variables further de?nitions v saw = instantaneous sawtooth voltage (pin 22) normally; 0 < v saw < 7.1 v; v cc = supply voltage applied to pin 12. v eht = eht compensation voltage applied to pin 1, normally between 1/2 v cc and 1/7 v cc . v off = internal offset voltage. v int = internal reference voltage of 7.1 v (also on pin 4) if the trapezium function (t) compensates for the internal offset voltage then the actual formula for z will simplify to: z = - 1 + 2v saw /v int since 0 v < v saw < 7.1 v, this is simply a negative going sawtooth and it follows that: - 1 < z < 1. a: picture height 0 < a < 1 64 steps (6 bits) y: v-linearity 0 < y < 1 64 steps (6 bits) s: v-s correction 0 < s < 1 64 steps (6 bits) d: v-shift 0 < d < 1 64 steps (6 bits) v: v-compensation 0 < v < 1 32 steps (5 bits) w: picture width 0 < w < 1 64 steps (6 bits) p: e-w parabola 0 < p < 1 64 steps (6 bits) c: e-w corner 0 < c < 1 64 steps (6 bits) t: trapezium 0 < t < 1 64 steps (6 bits) h: h-compensation 0 < h < 1 32 steps (5 bits) a = 0.80 (a + 2)/3 p = 0.55 p y = 0.17 y c = 0.38 c s = 0.42 s t = 0.32 (1 + 2t) volts d = 2.4 - 0.7 d volts e = (v cc / 2 - v eht ) / 42 w = 0.16 w z = - 1 + 2 x (v saw - t) v int
august 1991 19 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 vertical drive waveform the vertical drive waveform has certain interactions between the parameters whereby: the s-correction influences the picture height the linearity correction can influence the picture shift. the alignment can be made non-repetitive. once correct values for the v-s correction and v-linearity are set, the picture height may be changed without affecting the v-s correction and v-linearity on the screen. the formula for the vertical drive waveform at pin 21 is: v vert = d + 1.32 a {(z - sa 2 z 3 ) (1 - ve) + yz 2 } volts. picture height the amplitude of the sawtooth waveform is controlled by 'a'. it follows therefore that: 0.53 < a < 0.8 the nominal value for 'a' is found for a = 0.5, therefore a = 0.67. by programming the picture height, the sawtooth amplitude can be adjusted from - 19% to +19%. without s-correction (s = o) and linearity correction (y = o), the nominal sawtooth amplitude is (with a = 0.67); 1.32 x 0.67 x 2 = 1.77 v (p-p) v-linearity this function is meant to compensate for non-linearity of ac coupled vertical output stages. the linearity correction changes proportionally to the picture height setting. the range for linearity control is typically 17% of the peak-to-peak value of the linear sawtooth (see fig.7). v-s correction the range for the v-s correction (sa 2 ) is defined as a percentage of the undistorted peak-to-peak sawtooth voltage (see fig.7). the actual s-correction component (sa 2 ) is dependent on the picture height setting where: at maximum picture height (a = 0.80) : sa 2 = 0.282 at nominal picture height (a = 0.62) : sa 2 = 0.197 at minimum picture height (a = 0.53) : sa 2 = 0.125 picture shift the dc level of the output is fixed by 'd'. it can be adjusted within a range of - 19% to +19%. in actual application this will be used for shifting the picture vertically. v-compensation the vertical deflection can be modulated by the instantaneous value of the signal applied to the eht compensation input. this external signal should reflect the eht variations. the amount of deflection reduction is in the range 0 to 10%, if pin 24 is at (v cc / 2) - 4.3 v (maximum modulation i.e. 1.7 v typical). thus for maximum modulation, the v-drive waveform can be reduced to 90% of its value. there is no reduction when the eht-compensation input is at v cc / 2 v (i.e. 6 v typical). trapezium the trapezium function is the only ic-confined adjustment and is intended to compensate for any internal offsets. the function is called trapezium because of its effect on the picture if an ac-coupled vertical deflection stage is used. the trapezium function can alter the picture shift range by a maximum of 190 mv. if the trapezium function is used for purposes other than eliminating the internal offsets, then the v-linearity can affect the actual picture height. this can affect the symmetry of the s-correction which, in turn, can affect the v-linearity. e-w drive waveform in order to obtain independent control of the picture width, parabola function and the h-compensation on a screen each function has been designed to be dependent on the other two. with reference to fig.8, the voltage across the h-deflection stage is: v def1 = v supply (1 - w) (1 - p) (1 - e) where: this shows for instance, that the h-compensation is made dependent on the actual value of the parabola function. for a tv set which needs a large parabola compensation and, also, a large eht-compensation, this function allows an optimal eht-compensation independent of the parabola function. v supply = supply voltage for h-deflection stage w = picture width alignment p = parabola function e = h-compensation
august 1991 20 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 all correction voltages are related to the supply voltage. the TDA8433 is designed to accept a supply voltage of 30 v. normally higher voltages are employed therefore a voltage amplifier, with a gain of v supply /30, is used between the TDA8433 and the diode modulator. the formula for the e-w drive output voltage at pin 19 is: v e-w = 30 x {1 - (1 - w) (1 - pa 2 z 2 + ca 4 z 4 ) (1 - 1.1 x he)} + 1.8 v as can be seen from the formula, the picture width, parabola function and h-compensation are influenced by each other. the functions are discussed separately with the other compensations set to zero. picture width control (p-c-h-o) it is possible to change the picture width by adjusting 'w' from 0 to 0.16. thus the complete range for the picture control width is - 10 to +10%. by only changing the picture width control the output voltage at pin 19 can vary between 1.8 and 6.6 v typical. parabola function the parabola function is also dependent on the picture height function. the values given are valid for a nominal height setting (a = 0.67 v). the parabola function consists of two parts: a parabola part - e-w parabola is created by squaring a linear sawtooth. the range of this pure parabola varies from 0 to 25% typical i.e. the amplitude of the parabola waveform is programmable from 0 to 7.5 v (typical). a fourth order part - e-w corner is created by squaring the parabola. the range of this corner correction varies from 0 to 7% (typical) i.e. the amplitude of the corner correction waveform is programmable from 0 to - 2.2 v (typical). a negative output voltage is not possible. the e-w corner correction waveform has to be subtracted from one of the other alignment functions. the split-up into the e-w parabola and the e-w corner enables each television set to be aligned with straight vertical lines. the trapezium is also related to the parabola function. the main reason for the trapezium correction is to compensate for internal offsets in the geometry control part. therefore: the amount of trapezium correction is fully dependent on the amount of parabola correction and corner correction that is needed. with no parabola and corner correction the trapezium output will be zero. the maximum possible trapezium output is 1.6 v (typical - see fig.7). this is the case where: a = 0.5, c = 0 and p = 1 i.e. no corner correction and the maximum parabola correction at nominal picture height settings. h-compensation control the horizontal deflection can be modulated by the instantaneous value of the signal applied to the eht compensation input. this external signal should reflect the eht variations. the amount of deflection reduction is in the range 0 to 10% if the input at pin 7 is at (v supply /2) - 4.3 v (maximum modulation is 1.7 v typical). with maximum modulation this range corresponds to an output voltage of 0 to 3.3 v. there is no reduction when the eht-compensation input is at v supply /2 v (typical 6 v).
august 1991 21 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.8 application diagram of an ac coupled amplifier stage. fig.9 application diagram for driving the diode modulator.
august 1991 22 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.10 input/output pin-configuration of TDA8433 (continued in fig.11).
august 1991 23 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 fig.11 input/output pin-configuration of TDA8433 (continued from fig.10).
august 1991 24 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 package outline unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot101-1 92-11-17 95-01-23 a min. a max. b w m e e 1 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 3.9 3.4 0.25 2.54 15.24 15.80 15.24 17.15 15.90 2.2 5.1 0.51 4.0 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.15 0.13 0.01 0.10 0.60 0.62 0.60 0.68 0.63 0.087 0.20 0.020 0.16 051g02 mo-015ad m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. z max. (1) (1) (1) dip24: plastic dual in-line package; 24 leads (600 mil) sot101-1
august 1991 25 philips semiconductors product speci?cation de?ection processor for computer controlled tv receivers TDA8433 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.

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